/**
 * Copyright (C) 2021 - 2031 O-Cubes Co., Ltd.
 */

/****************************************************************
 *  @file    sdadc.h
 *  @brief   sdadc driver header file
 *  @version v1.0
 *  @date    12  Sep. 2023
 *  @author  liusg
 ****************************************************************/
#ifndef __SDADC_H__
#define __SDADC_H__


#include "bits.h"
#include "eocv100.h"
#include <stdbool.h>

#ifdef __cplusplus
extern "C" {
#endif

#define SDADC_REG_BASE                      MEM_MAP_SDADC_BASE_ADDR
#define SDADC                               ((SDADC_REG_PTR)SDADC_REG_BASE)

#define SDADC_ENABLE                        BIT(0)
#define SDADC_CHANS_PWR_ON                  (0U)
#define SDADC_CHANS_PWR_OFF                 (0xFFFFFFFFU)
#define SDADC_CHANS_ENABLE                  (0xFFU)
#define SDADC_REF_PWR_ON                    BIT(4)
#define SDADC_BAIS_PWR_ON                   BIT(0)
#define SDADC_PHASE_ENABLE                  BIT(31)
#define SDADC_PHASE_UDELAY_MASK             GENMASK(30, 24)
#define SDADC_PHASE_UDELAY_OFF              (24U)
#define SDADC_PHASE_IHDELAY_MASK            GENMASK(22, 16)
#define SDADC_PHASE_IHDELAY_OFF             (16U)
#define SDADC_PHASE_IMDELAY_MASK            GENMASK(14, 8)
#define SDADC_PHASE_IMDELAY_OFF             (8U)
#define SDADC_PHASE_ILDELAY_MASK            GENMASK(6, 0)
#define SDADC_PHASE_ILDELAY_OFF             (0U)
#define SDADC_ZL_PHASE_ENABLE               BIT(24)

#define SDADC_GAIN_CFG_BIT_SIZE             (8U)

typedef enum {
	SDADC_CHAN0,
	SDADC_CHAN1,
	SDADC_CHAN2,
	SDADC_CHAN3,
	SDADC_CHAN4,
	SDADC_CHAN5,
	SDADC_CHAN6,
	SDADC_CHAN_MAX,
} sdadc_chan;

typedef enum {
	SDADC_PHASE_A,
	SDADC_PHASE_B,
	SDADC_PHASE_C,
} sdadc_phase;

typedef struct sdadc_reg {
	__IOM uint32_t CHAN_EN;                       /*0x00*/
	__IOM uint32_t ADC_PHASE[3];                  /*0x04*/
	__IOM uint32_t ZL_PHASE;                      /*0x10*/
	__IOM uint32_t CHAN_PWR;                      /*0x14*/
	__IOM uint32_t CHAN_GAIN[2];                  /*0x18*/
	__IOM uint32_t ADC_CTRL;                      /*0x20*/
	__IOM uint32_t ADC_TEST;                      /*0x24*/
	__IM  uint32_t CHAN_DATA[4];                  /*0x28*/
	__OM  uint32_t ADC_ENBALE;                    /*0x38*/
	__IOM uint32_t ADC_TEST_MOD;                  /*0x3C*/
	__IOM uint32_t ADC_TEST_DATA;                 /*0x40*/
} SDADC_REG, *SDADC_REG_PTR;

void sdadc_bais_pwr_en(bool enable);
void sdadc_ref_pwr_en(bool enable);
void sdadc_chans_pwr_en(bool enable);
void sdadc_chans_en(bool enable);
void sdadc_enable(bool enable);
void sdadc_gain_cfg(sdadc_chan chan, uint8_t gain);
void sdadc_phase_en(sdadc_phase phase, bool enable);
void sdadc_phase_cfg(sdadc_phase phase, uint8_t u_delay, uint8_t ih_delay, uint8_t im_delay, uint8_t il_delay);
void sdadc_zl_phase_en(bool enable);
void sdadc_zl_phase_cfg(uint8_t ih_delay, uint8_t im_delay, uint8_t il_delay);
void sdadc_init(void);

#ifdef __cplusplus
}
#endif

#endif
